Binary, true/complement signal generation circuits are generally used to drive decoder circuits such as are required to decode the address signals for an array of storage elements. In the state-of-the-art semiconductor memory arrays, the overall storage cycle time is limited by the speed of the signal buffering circuits for address decoders, which must drive the large capacitive loads represented by the large plurality NOR decoder gates.
Prior art true/complement signal generation circuits have had their switching speed impaired by transferring this output capacitive loading back to the clock driving circuits which time the overall operation of the buffer circuit.